/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2020-2021.
 * Description: serial synopsys header file
 * Author: yanbo <joey.yanbo@huawei.com>
 * Create: 2020-11-19
 */
#ifndef __SERIAL_SYNOPSYS_H
#define __SERIAL_SYNOPSYS_H

#define    NO_DATA        0x00
#define    BREAK_ERROR    0x01
#define    NOMAL_ERROR    0x02
#define    RECV_OK        0x03


#define         SYNOPSYS_UART_TIMEOUT   10

#define SYNOPSYS_UART_DR              0x00              /* Data read or written from the interface. */

#define SYNOPSYS_UART_DLL               0x00
#define SYNOPSYS_UART_DLH               0x04

#define SYNOPSYS_UART_IER       0x04                    /* Interrupt enable register */
#define SYNOPSYS_UART_PTIME     (0x01 << 7)             /* THRE Interrupt switch */
#define SYNOPSYS_UART_EDSSI     (0x01 << 3)             /* modem status interrupt switch */
#define SYNOPSYS_UART_ELSI      (0x01 << 2)             /* receive line status interrupt switch */
#define SYNOPSYS_UART_ETBEI     (0x01 << 1)             /* transmit holding register empty interrupt switch */
#define SYNOPSYS_UART_ERBFI     (0x01 << 0)             /* receive data avliable interrupt switch */


#define SYNOPSYS_UART_IIR               0x08             /* interrupt indentify register */
#define SYNOPSYS_UART_IIR_MSR           0x00             /* modem status */
#define SYNOPSYS_UART_IIR_NOIRQ         0x01             /* No interrupt pending */
#define SYNOPSYS_UART_IIR_THRE          0x02             /* THR empty */
#define SYNOPSYS_UART_IIR_RECEN         0x04             /* receive data available */
#define SYNOPSYS_UART_IIR_RLS           0x06             /* receive line statues */
#define SYNOPSYS_UART_IIR_BUSY          0x07             /* busy detect */
#define SYNOPSYS_UART_IIR_TIMEOU        0x0C             /* character timeout */
#define	SYNOPSYS_UART_IIR_ANY           0x0F             /* all interrupt indentify flag */


#define SYNOPSYS_UART_FCR             0x08               /* FIFO control register */
#define SYNOPSYS_UART_FCR_RX_EM      (0x00 << 6)         /* one character in the fifo */
#define SYNOPSYS_UART_FCR_RX1_4      (0x01 << 6)         /* 1/4 fifo */
#define SYNOPSYS_UART_FCR_RX1_2      (0x02 << 6)         /* 1/2 fifo */
#define SYNOPSYS_UART_FCR_RX_FF      (0x03 << 6)         /* 2 less than full */
#define SYNOPSYS_UART_FCR_TX_EM      (0x00 << 4)         /* empty */
#define SYNOPSYS_UART_FCR_TX_FF      (0x01 << 4)         /* 2 less than full */
#define SYNOPSYS_UART_FCR_TX1_4      (0x02 << 4)         /* 1/4 fifo */
#define SYNOPSYS_UART_FCR_TX1_2      (0x03 << 4)         /* 1/2 fifo */
#define SYNOPSYS_UART_FCR_DMAE       (0x01 << 3)         /* DMA enable */
#define SYNOPSYS_UART_FCR_XMIT       (0x01 << 2)         /* XMIT FIFO Reset */
#define SYNOPSYS_UART_FCR_RCVR       (0x01 << 1)         /* RCVR FIFO Reset */
#define SYNOPSYS_UART_FCR_EN         (0x01 << 0)         /* FIFO enable */


#define SYNOPSYS_UART_LCR               0x0C             /* line control register */
#define SYNOPSYS_UART_LCR_DLAB          (0x01 << 7)      /* Divisor Latch Access Bit */
#define SYNOPSYS_UART_LCR_BC            (0x01 << 6)      /* Break Control Bit */
#define SYNOPSYS_UART_LCR_EPS           (0x01 << 4)      /* Even Parity Select */
#define SYNOPSYS_UART_LCR_PEN           (0x01 << 3)      /* Parity enable bit */
#define SYNOPSYS_UART_LCR_STOP          (0x01 << 2)      /* stop bit */
#define SYNOPSYS_UART_LCR_DLS5          0x00             /* Data Length Select 5bits */
#define SYNOPSYS_UART_LCR_DLS6          0x01             /* Data Length Select 6bits */
#define SYNOPSYS_UART_LCR_DLS7          0x02             /* Data Length Select 7bits */
#define SYNOPSYS_UART_LCR_DLS8          0x03             /* Data Length Select 8bits */


#define SYNOPSYS_UART_MCR               0x10             /* modem control register */
#define SYNOPSYS_UART_MCR_SIRE          (0x01 << 6)      /* IrDA SIR Mode switch */
#define SYNOPSYS_UART_MCR_ACFE          (0x01 << 5)      /* Auto Flow Control Mode switch */
#define SYNOPSYS_UART_MCR_LB            (0x01 << 4)      /* LoopBack Bit */
#define SYNOPSYS_UART_MCR_OUT2          (0x01 << 3)      /* out2 */
#define SYNOPSYS_UART_MCR_OUT1          (0x01 << 2)      /* out1 */
#define SYNOPSYS_UART_MCR_RTS           (0x01 << 1)      /* request to send */
#define SYNOPSYS_UART_MCR_DTR           (0x01 << 0)      /* data Terminal ready */


#define SYNOPSYS_UART_LSR               0x14
#define SYNOPSYS_UART_LSR_RFE           (0x01 << 7)      /* Receiver FIFO Error bit */
#define SYNOPSYS_UART_LSR_TEMT          (0x01 << 6)      /* Transmitter Empty bit */
#define SYNOPSYS_UART_LSR_THRE          (0x01 << 5)      /* Transmit Holding Register Empty bit */
#define SYNOPSYS_UART_LSR_BI            (0x01 << 4)      /* Break Interrupt bit. */
#define SYNOPSYS_UART_LSR_FE            (0x01 << 3)      /* Framing Error bit. */
#define SYNOPSYS_UART_LSR_PE            (0x01 << 2)      /* Parity Error bit. */
#define SYNOPSYS_UART_LSR_OE            (0x01 << 1)      /* Overrun error bit */
#define SYNOPSYS_UART_LSR_DR            (0x01 << 0)      /* Data Ready bit. */
#define SYNOPSYS_RSR_ANY                (SYNOPSYS_UART_LSR_BI|SYNOPSYS_UART_LSR_FE \
						|SYNOPSYS_UART_LSR_PE|SYNOPSYS_UART_LSR_OE)

#define SYNOPSYS_UART_STATUS            0x7C
#define SYNOPSYS_UART_STATUS_RFF        (0x01 << 4)     /* Receive FIFO Full flag */
#define SYNOPSYS_UART_STATUS_RFNE       (0x01 << 3)     /* Receive FIFO not empty */
#define SYNOPSYS_UART_STATUS_TFE        (0x01 << 2)     /* Transmit FIFO Empty */
#define SYNOPSYS_UART_STATUS_TFNF       (0x01 << 1)     /* Transmit FIFO Not Full */
#define SYNOPSYS_UART_STATUS_BUSY       (0x01 << 0)     /* busy */

#endif
